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t66h0004a tm technology inc. reserves the right p. 1 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch t66h0004a 80 output lcd segment/common driver ic description the t66h0004a is a lcd driver lsi which is fabricated by low power cmos high voltage process technology. in segment driver mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. in common driver mode, dual type mode is applicable. and in segment mode application, the power down function reduces power consumption. features power supply voltage: +5v10% to +3v10% supply voltage for display: 6 to 28v(v dd -v ee ) 4 bit parallel/1 bit serial data processing (in segment mode) single mode operation/dual mode operation (in common mode) power down function (in segment mode) applicable lcd duty:1/64 ? 1/256 high voltage cmos process bare die , qfp or tqfp available ordering information part no. pkg. description T66H0004A-Q qfp 100 pin t66h0004a-t tqfp 100 pin t66h0004a1s cog refer to pads list
t66h0004a tm technology inc. reserves the right p. 2 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch package information qfp 100qfp package 52 53 54 55 sc1 sc2 sc3 sc4 sc5 57 58 59 sc6 sc7 sc8 sc9 sc10 62 63 64 65 sc11 sc12 sc13 sc14 sc15 67 68 69 sc16 sc17 sc18 sc19 sc20 72 73 74 75 sc21 sc22 sc23 sc24 sc25 77 78 79 80 sc26 sc27 sc28 sc29 sc30 29 28 27 26 sc80 sc79 sc78 sc77 sc76 24 23 22 21 sc75 sc74 sc73 sc72 sc71 19 18 17 16 sc70 sc69 sc68 sc67 sc66 14 13 12 11 sc65 sc64 sc63 sc62 sc61 9 8 7 6 sc60 sc59 sc58 sc57 sc56 4 3 2 1 sc55 sc54 sc53 sc52 sc51 50 d1_sid cl2 ams cl1 elb 45 shl vss d4_dr d3_dm d2_dl 49 48 47 46 44 43 42 41 40 v0 cs m d_off vdd 35 erb vee v5 v43 v12 39 38 37 36 34 33 32 31 81 sc35 sc34 sc33 sc32 sc31 86 sc40 sc39 sc38 sc37 sc36 82 83 84 85 87 88 89 90 91 sc45 sc44 sc43 sc42 sc41 96 sc50 sc49 sc48 sc47 sc46 92 93 94 95 97 98 99 100 66 61 51 56 60 5 10 15 20 25 30 70 71 76 T66H0004A-Q
t66h0004a tm technology inc. reserves the right p. 3 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch tqfp 100tqfp package 52 53 54 55 sc78 sc79 57 58 59 62 63 64 65 67 68 69 72 73 74 75 24 23 22 21 sc52 sc51 sc50 sc49 sc48 19 18 17 16 sc47 sc46 sc45 sc44 sc43 14 13 12 11 sc42 sc41 sc40 sc39 sc38 9 8 7 6 sc37 sc36 sc35 sc34 sc33 4 3 2 1 sc32 sc31 sc30 sc29 sc28 50 d1_sid cl2 ams cl1 elb 45 shl vss d4_dr d3_dm d2_dl 49 48 47 46 44 43 42 41 40 d_off vdd 35 erb vee 39 38 37 36 34 33 32 31 81 sc12 sc11 sc10 sc9 sc8 86 sc17 sc16 sc15 sc14 sc13 82 83 84 85 87 88 89 90 91 sc22 sc21 sc20 sc19 sc18 96 sc27 sc26 sc25 sc24 sc23 92 93 94 95 97 98 99 100 66 61 51 56 60 5 10 15 20 25 70 71 t66h0004a-t v0 cs 28 v5 v43 v12 30 29 27 26 76 sc7 sc6 sc5 sc4 sc3 77 78 79 80 sc53 sc54 sc55 sc56 sc57 sc58 sc59 sc60 sc61 sc62 sc63 sc64 sc65 sc66 sc67 sc68 sc69 sc70 sc71 sc72 sc73 sc74 sc75 sc76 sc77 sc1 sc2 sc80 m
t66h0004a tm technology inc. reserves the right p. 4 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch block diagram
t66h0004a tm technology inc. reserves the right p. 5 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch block description name function com/seg clock control generates latch clock (lck),shift clock(sck) and control clock timing according to the input of cl1,cl2 and control inputs(cs,ams). in common driver application mode, this block generates the shift clock (lck) for the common data bi-directional shift register. com/seg data latch control determines the direction of segment data shift, and input data of each bi-directional shift register. in 4-bit segment data parallel transfer mode, data is shifted by 4-bit unit. in common driver application mode, data is transferred to the common data shift register directly, which disables this block. seg power down function controls the clock enable state of the current driver according to the input value of enable pin (elb or erb). if enable input value is ?low?, every clock of the current driver is enabled and the clock control block works. but if enable input is ?high?, current driver is disabled and the input data value has no effect on the output level. so power consumption can be lowered. seg output level selector controls the output voltage level according to the input control pin (m and dispoffb) (refer to pin description). com/seg 20x4-bit segment data bi-directional shift register stores output data value by shifting the input values. in 1-bit serial interface mode application, all 80 shift clocks (sck) are needed to store all the display data. but in 4-bit parallel transfer mode application, only 20 clocks are needed. in common driver application mode, this block does not work. seg 80?bit data latch/common data bi-directional shift register in segment driver application mode, the data from the 20x4-bit segment data shift register are latched for segment driver output. in single-type common driver application, 1-bit input data (from dl or dr pin) is shifted and latched by the direction according to the shl signal input. in dual-type common application mode, 80-bit registers are divided by two blocks and controlled independently (refer to note 3). com/seg 80-bit level shifter voltage level shifter block for high voltage part. the inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. these values are output to the driver. seg 80-bit 4-level driver selects the output voltage level according to m and latched data value. if the data value is ?high? the driver output is at selected voltage level (v0 or v5), and in the reverse case the driver output value is at the non-selected level (v12 or v43). in segment driver application mode, non-selected output value is v2 or v3. and when in common driver application, this value becomes v1 or v4. seg
t66h0004a tm technology inc. reserves the right p. 6 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch pin description pin i/o name function interface v dd logical ?high? input port(+5v10%,+3v10%) vss 0v(gnd) v ee power supply logical ?low? for high voltage part power v0,v12, v43,v5 i lcd driver output voltage level bias supply voltage input to drive the lcd. bias voltage divided by the resistance is usually used as a supply voltage source (refer to note 2). power sc1-sc80 o lcd driver output display data output pin which corresponds to the respective latch contents. one of v0, v12, v34 and v5 is selected as a display driving voltage source according to the combination of the latch data level and m signal (refer to note 1). lcd cl2 i data shift clock clock pulse input for the bi-directional shift register. - in segment driver application mode, the data is shifted to 20x4-bit segment data shift. the clock pulse, which was input when the enable bit (elb/erb) is in not active condition, is invalid. - in common driver application mode, the data is shifted to 80-bit common data bi-directional shift register by the cl1 clock. hence, this clock pin is not used (open or connect this pin to vdd). controller m i ac signal for lcd driver output alternate signal input pin for lcd driving. normal frame inversion signal is input in to this pin. controller cl1 i data latch clock - in segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. cl1 pulse ?high? level initializes power-down function block. - in common driver application mode, cl1 is used as a shifting clock of common output data. controller dispoffb i display off control control input pin to fix the driver output (sc1-sc80) to v0 level, during ?low? value input. lcd becomes non-selected by v0 level output from every output of segment drivers and every output of common drivers. controller cs i com/seg mode control when cs = ?low?, t66h0004a is used as an 80-bit segment driver. when cs = ?high?, t66h0004a is set to an 80-bit common driver. vdd/vss according to the input value of the ams and the cs pin, application mode of t66h0004a is differs as shown below. cs ams application mode 0 0 4-bit parallel interface mode 0 1 1-bit serial interface mode seg 1 0 single type application mode ams i application mode select 1 1 dual type application mode com vdd/vss d1_sid, d2_dl, i/o display data in p ut/serial - in segment driver application mode, these pins are used as 4-bit data in p ut p in ( when 4-bit p arallel controller
t66h0004a tm technology inc. reserves the right p. 7 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch d3_dm, d4_dr input data/left, right data input output interface mode: ams = ?low?), or d1_sid is used as serial data input pin and other pins are not used (connect these to vdd) (when 1-bit serial interface mode: ams = ?high?). - in common driver application mode, the data is shifted from d2_dl(d4_dr) to d4_dr (d2_dl),when in single type interface mode (ams = ?low?). in dual-type application case, the data are shifted from d2_dl and d3_dm (d4_dr and d3_dm) to d4_dr(d2_dl). in each case the direction of the data shift and the connection of data pins are determined by shl input (refer to note3, note4). shl input shift direction control when shl = ?low?, data is shifted from left to right. when shl = ?high?, the direction is reversed.(refer to note3) vdd/vss - in segment driver application mode, the internal operation is enabled only when enable input (elb or erb) is ?low? (power down function). when several drivers are serially connected, the enable state of each driver is shifted according to the shl input. connect these pins as below. segment driver shl elb erb l output(open) input(vss) h input(vss) output(open) elb,erb i/o enable data input/output - in common driver application mode, power down function is not used. open these pins.
t66h0004a tm technology inc. reserves the right p. 8 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch note 1. output level control output level(sc1-sc80) m latched data dispoffb seg mode com mode l l h v12(v2) v12(v1) l h h v0 v5 h l h v43(v3) v43(v4) h h h v5 v0 x x l v0 v0 note 2. lcd driving voltage application circuit (1) segment driver application(cs = ?low?) (2) common driver application(cs = ?high?)
t66h0004a tm technology inc. reserves the right p. 9 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch note 3. data shift direction according to control signals (1) when cs = ?low?(segment driver application) ams shl application mode data direction input pin l shift direction last data first data s c 1 s c 2 s c 3 s c 4 s c 7 3 s c 7 4 s c 7 5 s c 7 6 s c 7 7 s c 7 8 s c 7 9 s c 8 0 d d d d d d d d d 1 d 2 d 3 d 4 1 2 3 4 1 2 3 4 l h 4-bit parallel data transfer mode(seg) shift direction first data last data s c 1 s c 2 s c 3 s c 4 s c 7 3 s c 7 4 s c 7 5 s c 7 6 s c 7 7 s c 7 8 s c 7 9 s c 8 0 d d d d d d d d d 4 d 3 d 2 d 1 4 3 2 1 4 3 2 1 d1_sid, d2_dl, d3_dm, d4_dr l shift direction last data (d1_sid) first data s c 1 s c 2 s c 3 s c 4 s c 7 3 s c 7 4 s c 7 5 s c 7 6 s c 7 7 s c 7 8 s c 7 9 s c 8 0 h h 1-bit serial data transfer mode (seg) shift direction first data last data s c 1 s c 2 s c 3 s c 4 s c 7 3 s c 7 4 s c 7 5 s c 7 6 s c 7 7 s c 7 8 s c 7 9 s c 8 0 d1_sid d1 d2 d3 d4 d1 d2 d3 d4
t66h0004a tm technology inc. reserves the right p. 10 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch (2) when cs = ?high?(common driver application) ams shl application mode data direction input pin l shift direction s c 1 s c 2 s c 3 s c 3 8 s c 3 9 s c 4 0 s c 4 1 s c 4 2 s c 4 3 s c 7 8 s c 7 9 s c 8 0 d2_dl l h single-type application mode (com) shift direction s c 1 s c 2 s c 3 s c 3 8 s c 3 9 s c 4 0 s c 4 1 s c 4 2 s c 4 3 s c 7 8 s c 7 9 s c 8 0 d4_dr l shift direction s c 1 s c 2 s c 3 s c 3 8 s c 3 9 s c 4 0 s c 4 1 s c 4 2 s c 4 3 s c 7 8 s c 7 9 s c 8 0 d2_dl, d3_dm h h dual-type application mode (com) shift direction s c 1 s c 2 s c 3 s c 3 8 s c 3 9 s c 4 0 s c 4 1 s c 4 2 s c 4 3 s c 7 8 s c 7 9 s c 8 0 d4_dr, d3_dm input data ( d2 dl ) output data (d4_dr) input data ( d4 dr ) output data (d2_dl) input data 1 ( d2 _ dl ) output data (d4_dr) input data 2 (d3_dm) input data 1 (d4_dr) output data (d2_dl) input data 2 (d3_dm)
t66h0004a tm technology inc. reserves the right p. 11 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch note 4. usage of data pins data interface pin com/seg (cs pin) application mode (ams pin) shl d1_sid d2_dl d3_dm d4_dr 4-bit parallel interface mode(ams = ?low?) x d1(input) d2(input2) d3(input3) d4(input4) seg (cs = ?low?) 1-bit serial interface mode (ams = ?high?) x sid(input) connect to vdd l dl(input) dr(output) single-type application mode( ams = ?low?) h open dl(output) open dr(input) l dl(input1) dm(input2) dr(output2) com (cs = ?high?) dual-type application mode (ams = ?high?) h open dl(output2) dm(input2) dr(input1) maximum absolute limit characteristic symbol value unit power supply voltage vdd -0.3 to +7.0 driver supply voltage vlcd 0 to +30 input voltage vin -0.3 to vdd+0.3 v operating temperature topr -30 to +85 storage temperature tstg -55 to +150 *note: voltage greater than above may do damage to the circuit.
t66h0004a tm technology inc. reserves the right p. 12 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch electrical characteristics dc characteristics (1) segment driver applicatio n (vss = 0v, ta=-30 to +85 0 c) characteristic symbol test condition min. typ. max. unit v dd - 2.7 - 5.5 operating voltage 1 v lcd v in = v dd ?v ee 6 - 28 v ih - 0.8v dd - v dd input voltage (1) v i l - 0 - 0.2 v dd v v oh i oh = -0.4ma v dd -0.4 - - output voltage (2) v ol i ol = 0.4ma - - 0.4 v input leakage current 1 (1) i il1 v in = v dd to vss -10 - 10 input leakage current 2 (3) i il2 v in = v dd to v ee -25 - 25 ua on resistance (4) r on i on = 100ua - 2 4 k ohm i stby f cl1 =32 khz m=vss vss pin - - 50 ua v dd = 5v - - 5 i dd v dd = 3v - - 2 ma supply current (5) i ee f cl1 = 32khz f m = 80hz v dd =5v - - 500 ua notes: 1. applied to cl1,cl2,elb,erb,d1_sid-d4_dr,shl,dispoffb,m,cs,ams pin 2. elb,erb pin 3. v0,v12,v43,v5 pin 4. v lcd = v dd -v ee , v0=v dd =5v, v5=v ee =-23v v12 = v dd -2/n(v lcd ), v43= v ee +2/n(v lcd ), n=17(1/256 duty,1/17 bias) 5. v0= v dd , v12=1.71v(v dd =5v) or ?0.06v(v dd =3v) v43=-19.71v(v dd =5v) or ?19.94v(v dd =3v), v5=v ee =-23v, no-load condition (1/256 duty,1/17 bias) 4-bit parallel interface mode. istby: v dd =5v, cl2=vss, shl=vss, dispoffb= v dd , m = vss, display data pattern=0000 i dd : v dd =3v, f cl2 =4mhz, display data pattern=0101 v dd = 5v, f cl2 f cl2 =5.12mhz, display data pattern=0101 i ee : v dd =5v, f cl2 =5.12mhz, display data pattern=0101, v ee pin
t66h0004a tm technology inc. reserves the right p. 13 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch electrical characteristics (2) common driver application (vss = 0v, ta=-30 to +85 0 c) characteristic symbol test condition min. typ. max. unit v dd - 2.7 - 5.5 operating voltage v lcd v in = v dd ?v ee 6 - 28 v ih - 0.8 v dd - v dd input voltage (1) v il - 0 - 0.2 v dd v v oh i oh = -0.4ma v dd -0.4 - - output voltage (3) v ol i ol = 0.4ma - - 0.4 v input leakage current 1 (1) i il1 v in = v dd to vss -10 - 10 input leakage current 2 (2) i il2 v in =0, v dd =5v(pull up) -50 -125 -250 input leakage current 3 (4) i il3 v in = v dd to v ee -25 - 25 ua on resistance (5) r on i on = 100ua - 2 4 k ohm i stby f cl1 =32khz vss pin - - 50 v dd =5v - - 200 i dd v dd =3v - - 120 supply current(6) i ee f cl1 =32khz f m =80hz v dd =5v - - 150 ua notes: 1. applied to cl1, d2_dl (shl=low), d4_dr (shl=high), shl, dispoffb, m, cs, ams pin. 2. pull-up input pins: cl2, d1_sid, d3_dm (ams=high), elb (shl=low), erb (shl= high). 3. d2_dl (shl = high), d4_dr (shl = low) pin. 4. v0, v12, v43, v5 pin 5. v lcd = v dd -v ee , v0= v dd =5v,v5=v ee =-23v v12 = v dd -1/n(v lcd ), v43= v ee +1/n(v lcd ), n=17(1/256 duty, 1/17 bias) 6. v0= v dd , v12=3.35v(v dd =5v) or 1.47v(v dd =3v), v43=-21.35v(v dd =5v) or ?21.47v(v dd =3v), v5= v ee =-23v, no-load condition (1/256 duty, 1/17 bias)single-type mode operation: ams = vss, shl = vss, dispoffb = v dd d1_sid=d3_dm=vdd, d4_dr=open, elb+erb+open, i stby : v dd =5v, m=vss, d2_dl=vss i dd : f m =80hz, d2_dl= v dd v dd =3v, display data pattern=10000000?,01000000?,00100000?,00010000?,? v dd =5v.displat data pattern=10000000?,01000000?,00100000?,00010000?,? i ee : f m =80hz,d2_dl= v dd v dd =5v, current through v ee pin, display data pattern=100000000?,01000000?,00100000?,00010000?,?
t66h0004a tm technology inc. reserves the right p. 14 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch ac characterristics (1) segment driver application (vss = 0v, ta=-30 to +85 0 c) (1) vdd=5v10% (2) vdd=3v10% characteristic symbol test condition min. typ. max. min. typ. max. unit clock cycle time t cy duty=50% 125 - - 250 - - clock pulse width t wck - 45 - - 95 - - clock rise/fall time t r / t f - - - 30 - - 30 data set-up time t ds - 30 - - 65 - - data hold time t dh - 30 - - 65 - - clock set-up time t cs - 80 - - 120 - - clock hold time t ch - 80 - - 120 - - elb output 60 125 propagation delay time t phl erb output - - 60 - - 125 elb input 30 65 elb,erb set-up time t psu erb input 30 - - 65 - - ns dispoffb low pulse width t wdl - 1.2 - - 1.2 - - us dispoffb clear time t cd - 100 - - 100 - ns m-out propagation delay time t pd1 - - 1.0 - - 1.2 cl1-out propagation delay time t pd2 - - 1.0 - - 1.2 dispoffb-out propagation delay time t pd3 c l =15pf - - 1.0 - - 1.2 us latch pulse rise to shift clock rise time t ls 80 - - 120 - - ns
t66h0004a tm technology inc. reserves the right p. 15 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch ac characteristics (2) common driver application (vss = 0v, ta=-30 to +85 0 c) (1) vdd=5v10% (2) vdd=3v10% characteristic symbol test condition min. typ. max. min. typ. max. unit clock cycle time t cy duty=50% 250 - - 500 - - clock pulse width t wck - 45 - - 95 - - clock rise/fall time t r/ t f - - - 50 - - 50 data set-up time t ds - 30 - - 65 - - data hold time t dh - 30 - - 65 - - ns dispoffb low pulse width t wdl - 1.2 - - 1.2 - - us dispoffb clear time t cd - 100 - - 100 - output delay time t dl - - 200 - - 250 ns m-out propagation delay time t pd1 - - 1.0 - - 1.2 cl1-out propagation delay time t pd2 - - 1.0 - - 1.2 dispoffb-out propagation delay time t pd3 c l =15pf - - 1.0 - - 1.2 us
t66h0004a tm technology inc. reserves the right p. 16 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch ac characteristics (3) segment driver application timing
t66h0004a tm technology inc. reserves the right p. 17 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch ac characteristics (4) common driver application timing
t66h0004a tm technology inc. reserves the right p. 18 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch power down function in the case of cascade connection of segment mode drivers,t66h0004a has a ?power down function? in order to reduce the power consumption. shl enable input enable output current driver status the other drivers status l erb elb while erb = ?low?, current driver is enabled. disabled h elb erb while elb = ?low?, current driver is enabled disabled * in the case of common driver application, power down function dose not work.
t66h0004a tm technology inc. reserves the right p. 19 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch operation timing diagram (1) 4-bit parallel mode interface segment driver when shl = ?high? when shl = ?low?
t66h0004a tm technology inc. reserves the right p. 20 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch (2) 1-bit serial mode interface segment driver when shl = high? when shl = ?low?
t66h0004a tm technology inc. reserves the right p. 21 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch (3) single-type interface mode common driver when shl = ?low? when shl = ?high?
t66h0004a tm technology inc. reserves the right p. 22 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch (4) dual-type interface mode common driver when shl = ?low? when shl = ?high?
t66h0004a tm technology inc. reserves the right p. 23 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch (5) common/segment driver timing(1/200 duty)
t66h0004a tm technology inc. reserves the right p. 24 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch application information 1-bit serial interface mode (80 output segment driver) (a) lower view(shl = l , ams = h ) (b)upper view (shl = h, ams = h)
t66h0004a tm technology inc. reserves the right p. 25 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch 4-bit parallel interface mode (80 output segment driver) (a) lower view(shl = l , ams = l) (b) upper view (shl = h , ams = l)
t66h0004a tm technology inc. reserves the right p. 26 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch single-type interface mode (80 output common driver)
t66h0004a tm technology inc. reserves the right p. 27 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch dual-type interface mode (40 output common driver) note: using this application mode (dual-type common mode), the duty ratio can be reduced to half. in case, 1/200 duty can be used to drive the 400 common lcd panel.
t66h0004a tm technology inc. reserves the right p. 28 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch application circuit example
t66h0004a tm technology inc. reserves the right p. 29 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch package dimension (unit: mm) 100 pin tqfp
t66h0004a tm technology inc. reserves the right p. 30 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch 100 pin qfp
t66h0004a tm technology inc. reserves the right p. 31 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch pad list (for t66h0004a1s use) pad no. pin name x y pad no. pin name x y 1 y51 -1127.2 1473.25 36 vop:p -449.75 -1534.4 2 y52 -1127.2 1373.25 37 cs -349.75 -1534.4 3 y53 -1127.2 1273.25 38 m -249.75 -1534.4 4 y54 -1127.2 1173.25 39 disspo -149.75 -1534.4 5 y55 -1127.2 1073.25 40 vdd -49.75 -1534.4 6 y56 -1127.2 973.25 41 shl 50.25 -1534.4 7 y57 -1127.2 873.25 42 vss 150.25 -1534.4 8 y58 -1127.2 773.25 43 d4_dr 250.25 -1534.4 9 y59 -1127.2 673.25 44 d3_dm 350.25 -1534.4 10 y60 -1127.2 573.25 45 d2_dl 450.25 -1534.4 11 y61 -1127.2 473.25 46 d1_sid 550.25 -1534.4 12 y62 -1127.2 373.25 47 cl2 650.25 -1534.4 13 y63 -1127.2 273.25 48 ams 750.25 -1534.4 14 y64 -1127.2 173.25 49 cl1 850.25 -1534.4 15 y65 -1127.2 73.25 50 elb 950.25 -1534.4 16 y66 -1127.2 -26.75 51 y1 1127.7 -1426.7 5 17 y67 -1127.2 -126.75 52 y2 1127.7 -1326.7 5 18 y68 -1127.2 -226.75 53 y3 1127.7 -1226.7 5 19 y69 -1127.2 -326.75 54 y4 1127.7 -1126.7 5 20 y70 -1127.2 -426.75 55 y5 1127.7 -1026.7 5 21 y71 -1127.2 -526.75 56 y6 1127.7 -926.75 22 y72 -1127.2 -626.75 57 y7 1127.7 -826.75 23 y73 -1127.2 -726.75 58 y8 1127.7 -726.75 24 y74 -1127.2 -826.75 59 y9 1127.7 -626.75 25 y75 -1127.2 -926.75 60 y10 1127.7 -526.75 26 y76 -1127.2 -1026.7 5 61 y11 1127.7 -426.75 27 y77 -1127.2 -1126.7 5 62 y12 1127.7 -326.75 28 y78 -1127.2 -1226.7 5 63 y13 1127.7 -226.75 29 y79 -1127.2 -1326.7 5 64 y14 1127.7 -126.75 30 y80 -1127.2 -1426.7 5 65 y15 1127.7 -26.75 31 erb -949.75 -1534.4 66 y16 1127.7 73.25 32 veep:g -849.75 -1534.4 67 y17 1127.7 173.25
t66h0004a tm technology inc. reserves the right p. 32 publication date: mar. 2004 to change products or specifications without notice. revision:a tm te ch 33 v5p -749.75 -1534.4 68 y18 1127.7 273.25 34 v43p -649.75 -1534.4 69 y19 1127.7 373.25 35 v12p -549.75 -1534.4 70 y20 1127.7 473.25 pad no. pin name x y 88 y38 250.25 1534.4 71 y21 1127.7 573.25 89 y39 150.25 1534.4 72 y22 1127.7 673.25 90 y40 50.25 1534.4 73 y23 1127.7 773.25 91 y41 -49.75 1534.4 74 y24 1127.7 873.25 92 y42 -149.75 1534.4 75 y25 1127.7 973.25 93 y43 -249.75 1534.4 76 y26 1127.7 1073.25 94 y44 -349.75 1534.4 77 y27 1127.7 1173.25 95 y45 -449.75 1534.4 78 y28 1127.7 1273.25 96 y46 -549.75 1534.4 79 y29 1127.7 1373.25 97 y47 -649.75 1534.4 80 y30 1127.7 1473.25 98 y48 -749.75 1534.4 81 y31 950.25 1534.4 99 y49 -849.75 1534.4 82 y32 850.25 1534.4 100 y50 -949.75 1534.4 83 y33 750.25 1534.4 84 y34 650.25 1534.4 chip size ==> 85 y35 550.25 1534.4 ( 2349.4,3163.8 ) 86 y36 450.25 1534.4 87 y37 350.25 1534.4 y31 y50 y51 y80 y30 y1 elb cl1 ams cl2 d1_sid d2_dl d3_dm d4_dr vss shl vdd dispoff m cs v0 v12 v43 v5 vee erb t66h0004a1s

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